Design of the DUPLEX machine

Abstract

As computers become less expensive, interest in using CPUs to build novel parallel systems has increased. The goal is to achieve high parallelism at low cost. In this article, we first examine the reasons why we need graph reduction machine for the support of declarative languages to achieve high parallelism. The next is to survey recent development in graph reduction machines, to point out their strengths and weaknesses. Then we introduce a dual unit processing node architecture for the graph reduction machine that carefully separates the work load, as such one unit is responsible for network message handling and the other for supercombinator execution. Finally, we demonstrate that a highly parallel novel computer architecture is feasible at low cost.