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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/99283
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dc.titleFailure of instruction prefetching of 8088/286/ 386 microprocessors in XT/AT systems
dc.contributor.authorLua, K.T.
dc.date.accessioned2014-10-27T06:02:31Z
dc.date.available2014-10-27T06:02:31Z
dc.date.issued1990-09
dc.identifier.citationLua, K.T. (1990-09). Failure of instruction prefetching of 8088/286/ 386 microprocessors in XT/AT systems. Microprocessing and Microprogramming 29 (2) : 97-106. ScholarBank@NUS Repository.
dc.identifier.issn01656074
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/99283
dc.description.abstractThe Intel 8088/286/386 microprocessors are designed with instruction prefetch and pipeline features to increase their bus utilization and system throughput. However, there are many occasions where these features fail and instruction executions are lengthened. The failure of 8088/286/386 instruction prefetch and pipeline working under PC/XT and PC/AT environment are studied in this paper. We investigate the effect of (i) memory refresh, (ii) the heavy bus utilization and (iii) memory access wiat state on the performance of the 8088/286/386 prefetchers. © 1990.
dc.sourceScopus
dc.subject80286
dc.subject80386
dc.subject8088
dc.subjectInstruction timing
dc.subjectPipeline
dc.subjectPrefetch
dc.typeArticle
dc.contributor.departmentINFORMATION SYSTEMS & COMPUTER SCIENCE
dc.description.sourcetitleMicroprocessing and Microprogramming
dc.description.volume29
dc.description.issue2
dc.description.page97-106
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

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