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Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISPSD.2007.4294961
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dc.titleSuperjunction power LDMOS on partial SOI platform
dc.contributor.authorChen, Y.
dc.contributor.authorBuddharaju, K.D.
dc.contributor.authorLiang, Y.C.
dc.contributor.authorSamudra, G.S.
dc.contributor.authorFeng, H.H.
dc.date.accessioned2014-10-07T04:50:39Z
dc.date.available2014-10-07T04:50:39Z
dc.date.issued2007
dc.identifier.citationChen, Y., Buddharaju, K.D., Liang, Y.C., Samudra, G.S., Feng, H.H. (2007). Superjunction power LDMOS on partial SOI platform. Proceedings of the International Symposium on Power Semiconductor Devices and ICs : 177-180. ScholarBank@NUS Repository. https://doi.org/10.1109/ISPSD.2007.4294961
dc.identifier.isbn1424410959
dc.identifier.issn10636854
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/84260
dc.description.abstractSuperjunction power LDMOS device implemented on the bulk Si substrate suffers from the substrate-assisted depletion (SAD) effect, which causes the charge imbalance, and thus limits the device performance. A new SJ-LDMOS structure integrated on the partial SOI (PSOI) platform is proposed in this paper, which eliminates the SAD completely and enables the making of SJ-LDMOS on bulk silicon substrate without sacrificing its electrical and thermal performance. The PSOI SJ-LDMOS was fabricated and characterized. The tested PSOI SJ-LDMOS exhibits a specific on-state resistance of 1.01mΩ-cm2 while the breakdown voltage is 72.3V. © 2007 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ISPSD.2007.4294961
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ISPSD.2007.4294961
dc.description.sourcetitleProceedings of the International Symposium on Power Semiconductor Devices and ICs
dc.description.page177-180
dc.description.codenPISDE
dc.identifier.isiut000249645200045
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