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Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIT.2012.6242479
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dc.titleStrained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N +/P junction formation and GeSnO 2 interfacial layer
dc.contributor.authorHan, G.
dc.contributor.authorSu, S.
dc.contributor.authorWang, L.
dc.contributor.authorWang, W.
dc.contributor.authorGong, X.
dc.contributor.authorYang, Y.
dc.contributor.authorIvana
dc.contributor.authorGuo, P.
dc.contributor.authorGuo, C.
dc.contributor.authorZhang, G.
dc.contributor.authorPan, J.
dc.contributor.authorZhang, Z.
dc.contributor.authorXue, C.
dc.contributor.authorCheng, B.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-10-07T04:50:18Z
dc.date.available2014-10-07T04:50:18Z
dc.date.issued2012
dc.identifier.citationHan, G.,Su, S.,Wang, L.,Wang, W.,Gong, X.,Yang, Y.,Ivana,Guo, P.,Guo, C.,Zhang, G.,Pan, J.,Zhang, Z.,Xue, C.,Cheng, B.,Yeo, Y.-C. (2012). Strained germanium-tin (GeSn) N-channel MOSFETs featuring low temperature N +/P junction formation and GeSnO 2 interfacial layer. Digest of Technical Papers - Symposium on VLSI Technology : 97-98. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/VLSIT.2012.6242479" target="_blank">https://doi.org/10.1109/VLSIT.2012.6242479</a>
dc.identifier.isbn9781467308458
dc.identifier.issn07431562
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/84231
dc.description.abstractGeSn nMOSFETs were demonstrated. Key highlights of this work include 400°C GeSn n +/p junction formation and GeSnO 2 interfacial layer formation, and their integration. GeSn n +/p junction demonstrate a high doping concentration of 10 20 cm -3 and a record high forward bias current of 320 A/cm 2. Substantially improved SS is achieved in GeSn nMOSFET in comparison with Ge control, which indicates the high quality of the GeSnO 2/GeSn interface. © 2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/VLSIT.2012.6242479
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/VLSIT.2012.6242479
dc.description.sourcetitleDigest of Technical Papers - Symposium on VLSI Technology
dc.description.page97-98
dc.description.codenDTPTE
dc.identifier.isiutNOT_IN_WOS
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