Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/83968
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dc.titleModeling RF MOSFETs after electrical stress using low-noise microstrip line layout
dc.contributor.authorKao, H.L.
dc.contributor.authorChin, A.
dc.contributor.authorLai, J.M.
dc.contributor.authorLee, C.F.
dc.contributor.authorChiang, K.C.
dc.contributor.authorMcAlister, S.P.
dc.date.accessioned2014-10-07T04:47:16Z
dc.date.available2014-10-07T04:47:16Z
dc.date.issued2005
dc.identifier.citationKao, H.L.,Chin, A.,Lai, J.M.,Lee, C.F.,Chiang, K.C.,McAlister, S.P. (2005). Modeling RF MOSFETs after electrical stress using low-noise microstrip line layout. Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium : 157-160. ScholarBank@NUS Repository.
dc.identifier.issn15292517
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83968
dc.description.abstractA novel microstrip line layout is developed to direct measure the min. noise figure (NF min) accurately instead of the complicated de-embedding procedure in conventional CPW line. Very low NF min of 1.05 dB at 10 GHz is directly measured in 16 gate fingers 0.18μm MOSFETs without any de-embedding. Based on the accurate NF min measurement, we have developed the self-consistent DC, S-parameters and NF min model to predict device characteristics after the continuous stress with good accuracy. © 2005 IEEE.
dc.sourceScopus
dc.subjectLifetime
dc.subjectModel
dc.subjectNF min
dc.subjectRF noise
dc.subjectStress
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
dc.description.page157-160
dc.identifier.isiutNOT_IN_WOS
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