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|dc.title||Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH 3 and thin AlN) and TaN/HfO 2 gate stack|
|dc.identifier.citation||Whang, S.J.,Lee, S.J.,Gao, F.,Wu, N.,Zhu, C.X.,Pan, J.S.,Tang, L.J.,Kwong, D.L. (2004). Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH 3 and thin AlN) and TaN/HfO 2 gate stack. Technical Digest - International Electron Devices Meeting, IEDM : 307-310. ScholarBank@NUS Repository.|
|dc.description.abstract||Ge-MOS devices (EOT ∼ 7.5 Å, J g ∼ 10 -3 A/cm 2) are fabricated on both n- & p-type Ge-substrates, using novel surface passivation and TaN/HfO 2 gate stack. Results show that the plasma-PH 3 treatment and thin AlN layer at HfO 2/Ge interface are effective to suppress the GeO formation, which is mainly formed during HfO 2 deposition, and prevent Ge out-diffusion, resulting in improved C-V characteristics for n-MOS device with extremely low leakage. Thermal stability study of TaN/HfO 2/Ge gate stack shows that low leakage with thin EOT can be obtained after post-anneal at 500°C and degradation is observed above 600°C. It is also observed that good Ge n +-p and p +-n diode characteristics are achieved by S/D activation at 500°C and 400°C, respectively. Both p- & n-MOSFETs are fabricated by conventional self aligned process with maximum temperature of 500°C. Compared to reported Si-MOSFETs, the mobility enhancement of 1.6X for hole and 1.8X for electron is observed with Ge-MOSFETs. © 2004 IEEE.|
|dc.contributor.department||ELECTRICAL & COMPUTER ENGINEERING|
|dc.description.sourcetitle||Technical Digest - International Electron Devices Meeting, IEDM|
|Appears in Collections:||Staff Publications|
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