Effects of microtrenching from polysilicon gate patterning on 0.13μm MOSFET device performance

Abstract

During polysilicon gate patterning, the energetic ions from the high density plasma (HDP) are reflected off the polysilicon sidewalls and causes the formation of microtrenching. Results show that microtrenching depends strongly on the pattern density. An optimized polysilicon etch recipe had to be established for gate pattering to minimize the structural dependence. Various combinations of Cl2 HBr, CF4 and O2 etch chemistry are used to evaluate sidewall profile for the 0.13μm device. TSupreme4 and Medici simulations are applied to assess the effect of microtrench depth on device performance and the results are used to establish the tolerable microtrenching specification. The simulated results agree with the published data but the structural dependence of microtrenching does not.