Please use this identifier to cite or link to this item:
https://doi.org/10.1109/.2005.1469207
DC Field | Value | |
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dc.title | Dual metal gate process by metal substitution of dopant-free polysilicon on high-K dielectric | |
dc.contributor.author | Park, C.S. | |
dc.contributor.author | Cho, B.J. | |
dc.contributor.author | Hwang, W.S. | |
dc.contributor.author | Loh, W.Y. | |
dc.contributor.author | Tang, L.J. | |
dc.contributor.author | Kwong, D.-L. | |
dc.date.accessioned | 2014-10-07T04:43:38Z | |
dc.date.available | 2014-10-07T04:43:38Z | |
dc.date.issued | 2005 | |
dc.identifier.citation | Park, C.S.,Cho, B.J.,Hwang, W.S.,Loh, W.Y.,Tang, L.J.,Kwong, D.-L. (2005). Dual metal gate process by metal substitution of dopant-free polysilicon on high-K dielectric. Digest of Technical Papers - Symposium on VLSI Technology 2005 : 48-49. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/.2005.1469207" target="_blank">https://doi.org/10.1109/.2005.1469207</a> | |
dc.identifier.issn | 07431562 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/83651 | |
dc.description.abstract | Dual metal gate integration scheme of using substituted Al (SA) and Pt xSi with high Pt concentration on high-K dielectric is proposed. The process can achieve a wide range of work function difference (0.65 eV) and is almost free from Fermi level pinning, without adverse effects of polysilicon pre-doping. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/.2005.1469207 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/.2005.1469207 | |
dc.description.sourcetitle | Digest of Technical Papers - Symposium on VLSI Technology | |
dc.description.volume | 2005 | |
dc.description.page | 48-49 | |
dc.description.coden | DTPTE | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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