Please use this identifier to cite or link to this item: https://doi.org/10.1109/FPL.2013.6645513
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dc.titleCriticality-based routing for FPGAS with reverse body bias switch box architectures
dc.contributor.authorLoke, W.T.
dc.contributor.authorZhao, W.
dc.contributor.authorHa, Y.
dc.date.accessioned2014-10-07T04:42:58Z
dc.date.available2014-10-07T04:42:58Z
dc.date.issued2013
dc.identifier.citationLoke, W.T.,Zhao, W.,Ha, Y. (2013). Criticality-based routing for FPGAS with reverse body bias switch box architectures. 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings : -. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/FPL.2013.6645513" target="_blank">https://doi.org/10.1109/FPL.2013.6645513</a>
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83593
dc.description.abstractThe use of reverse body bias (RBB) in circuit design is recognized to be a viable strategy for managing leakage power, a burning issue as process nodes continue to shrink beyond the 20nm realm. This technique is especially useful to FP-GAs, which are able to tune RBB modes on-the-fly, offering leakage power reduction with very little impact to circuit speed. Most works today on RBB as applied to FPGAs are limited to the optimizations at the CLB level. We present a different architectural enhancement - the RBB switch box, and a routing algorithm deploying net criticality ranking that exploits the flexibility of such an architecture. Compared to the non-RBB baseline, our scheme yields an average of 64.74% and 38.92% savings in the routing leakage power and the total power respectively (contributed solely by our routing architecture), with slight improvements to timing. The area overhead associated with our enhancement is also very small, with one unit area of biasing circuit 140×100μm 2 supporting ∼340 switch boxes i.e. a 13×13 CLB array. © 2013 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/FPL.2013.6645513
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/FPL.2013.6645513
dc.description.sourcetitle2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings
dc.description.page-
dc.identifier.isiutNOT_IN_WOS
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