Please use this identifier to cite or link to this item:
https://doi.org/10.1109/ASSCC.2013.6691030
DC Field | Value | |
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dc.title | A wireless power management and data telemetry circuit module for high compliance voltage electrical stimulation applications | |
dc.contributor.author | Zhao, J. | |
dc.contributor.author | Yao, L. | |
dc.contributor.author | Xue, R.-F. | |
dc.contributor.author | Peng, L. | |
dc.contributor.author | Je, M. | |
dc.contributor.author | Xu, Y.P. | |
dc.date.accessioned | 2014-10-07T04:41:10Z | |
dc.date.available | 2014-10-07T04:41:10Z | |
dc.date.issued | 2013 | |
dc.identifier.citation | Zhao, J.,Yao, L.,Xue, R.-F.,Peng, L.,Je, M.,Xu, Y.P. (2013). A wireless power management and data telemetry circuit module for high compliance voltage electrical stimulation applications. Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 : 253-256. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ASSCC.2013.6691030" target="_blank">https://doi.org/10.1109/ASSCC.2013.6691030</a> | |
dc.identifier.isbn | 9781479902781 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/83432 | |
dc.description.abstract | A wireless power management and data telemetry circuit module for high compliance voltage electrical stimulation applications is presented in this paper. The system consists of rectifier, LDOs, DC-DC step-up charge pump and power monitoring circuit for closed loop wireless power management. The system also consists of a clock and data recovery (CDR) circuit and load shift keying (LSK) modulator for bidirectional data telemetry. The system operates at 13.56MHz. The wireless power management block receives AC power through an implantable coil and outputs three DC levels: 1V, 1.8V and 10V. The CDR circuit recovers clock and data from the 13.56MHz RF carrier through the same coil. The power efficiency of the wireless power management system is measured as 42% with 100μA current load connected on each supply output. The forward and backward data rate of the data telemetry achieves 61.5 kbps and 33.3 kbps, respectively. The system is implemented in 0.18μm CMOS process with 24V HV LDMOS option, occupying a core area of 1.8 mm × 1.8 mm. © 2013 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ASSCC.2013.6691030 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/ASSCC.2013.6691030 | |
dc.description.sourcetitle | Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, A-SSCC 2013 | |
dc.description.page | 253-256 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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