Please use this identifier to cite or link to this item:
https://doi.org/10.1109/EDSSC.2007.4450153
DC Field | Value | |
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dc.title | A novel technique to enhance the negative resistance for colpitts oscillators by parasitic cancellation | |
dc.contributor.author | Chen, Y. | |
dc.contributor.author | Mouthaan, K. | |
dc.contributor.author | Ooi, B.-L. | |
dc.date.accessioned | 2014-10-07T04:40:53Z | |
dc.date.available | 2014-10-07T04:40:53Z | |
dc.date.issued | 2007 | |
dc.identifier.citation | Chen, Y.,Mouthaan, K.,Ooi, B.-L. (2007). A novel technique to enhance the negative resistance for colpitts oscillators by parasitic cancellation. IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 : 425-428. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/EDSSC.2007.4450153" target="_blank">https://doi.org/10.1109/EDSSC.2007.4450153</a> | |
dc.identifier.isbn | 1424406374 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/83407 | |
dc.description.abstract | The oscillation frequency of conventional common collector Colpitis oscillators is limited due to the parasitic base collector capacitance C bc and base emitter capacitance Cbe- The Miller effect from the parasitic capacitance Cbc significantly reduces the negative resistance. Therefore, it is difficult to achieve sufficient negative resistance at higher frequencies to overcome resonator losses. In this paper, a novel technique is presented to enhance the negative resistance for common collector Colpitts oscillators. First, we analyze the effect of the collector inductor on the negative resistance. Then, we present a novel technique using an inductor to increase the negative resistance further. Then we discuss the effect of the Q-factor of these inductors on the negative resistance. To prove the technique, two Colpitts oscillators were designed at 400 MHz using discrete components. The measured phase noise is -110.19 dBc/Hz and -122.81 dBc/Hz at 100 kHz offset from 400 MHz and 410 MHz respectively and a RF output power of +0.62 dBm and +4.0 dBm respectively directly into single-ended 50 Ω load. ©2007 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/EDSSC.2007.4450153 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/EDSSC.2007.4450153 | |
dc.description.sourcetitle | IEEE Conference on Electron Devices and Solid-State Circuits 2007, EDSSC 2007 | |
dc.description.page | 425-428 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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