Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISCAS.2005.1464608
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dc.titleA novel DC-offset cancelling circuit for DCR
dc.contributor.authorYan, J.
dc.contributor.authorZheng, Y.
dc.contributor.authorXu, Y.P.
dc.date.accessioned2014-10-07T04:40:44Z
dc.date.available2014-10-07T04:40:44Z
dc.date.issued2005
dc.identifier.citationYan, J.,Zheng, Y.,Xu, Y.P. (2005). A novel DC-offset cancelling circuit for DCR. Proceedings - IEEE International Symposium on Circuits and Systems : 396-399. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ISCAS.2005.1464608" target="_blank">https://doi.org/10.1109/ISCAS.2005.1464608</a>
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83394
dc.description.abstractThis paper describes a novel DC-offset canceling structure for Direct-Conversion Receiver (DCR). The proposed structure uses an I/Q tuning loop to remove DCoffset. I/Q mismatch issue is discussed and according solution to suppress I/Q mismatch effects is adopted. A variable bandwidth technique is employed to accelerate the loop acquisition when the system is first time turned on. Simulation results show that the differential DC-offset voltage is less than 3mV after the loop becomes locked when a DC-offset of 100mV is presented. Moreover, the tuning loop can efficiently suppress effects of I/Q mismatch. © 2005 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ISCAS.2005.1464608
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ISCAS.2005.1464608
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.page396-399
dc.description.codenPICSD
dc.identifier.isiutNOT_IN_WOS
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