Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIT.2012.6242477
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dc.titleA new liner stressor (GeTe) featuring stress enhancement due to very large phase-change induced volume contraction for p-channel FinFETs
dc.contributor.authorCheng, R.
dc.contributor.authorDing, Y.
dc.contributor.authorKoh, S.-M.
dc.contributor.authorGyanathan, A.
dc.contributor.authorBai, F.
dc.contributor.authorLiu, B.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-10-07T04:40:36Z
dc.date.available2014-10-07T04:40:36Z
dc.date.issued2012
dc.identifier.citationCheng, R.,Ding, Y.,Koh, S.-M.,Gyanathan, A.,Bai, F.,Liu, B.,Yeo, Y.-C. (2012). A new liner stressor (GeTe) featuring stress enhancement due to very large phase-change induced volume contraction for p-channel FinFETs. Digest of Technical Papers - Symposium on VLSI Technology : 93-94. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/VLSIT.2012.6242477" target="_blank">https://doi.org/10.1109/VLSIT.2012.6242477</a>
dc.identifier.isbn9781467308458
dc.identifier.issn07431562
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/83383
dc.description.abstractWe report the first demonstration of a novel GeTe liner stressor which exhibits very large volume contraction during phase-change, and its integration in p-channel FinFETs for strain engineering. Conformally grown GeTe liner with different thicknesses was formed on FinFETs with ultra-scaled gate length L G down to ∼3 nm. When GeTe changes phase from amorphous (α-GeTe) to crystalline state (c-GeTe), GeTe liner contracts and compresses the Si source/drain region in the fin, leading to very high channel stress. Significant drive current I Dsat enhancement of 69% and 106% were observed for FinFETs with 30 nm and 50 nm c-GeTe liner stressor over the control devices, respectively. © 2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/VLSIT.2012.6242477
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/VLSIT.2012.6242477
dc.description.sourcetitleDigest of Technical Papers - Symposium on VLSI Technology
dc.description.page93-94
dc.description.codenDTPTE
dc.identifier.isiutNOT_IN_WOS
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