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Title: A 0.5-V 1.13-μW/channel neural recording interface with digital multiplexing scheme
Authors: Liew, W.-S. 
Zou, X. 
Lian, Y. 
Issue Date: 2011
Citation: Liew, W.-S.,Zou, X.,Lian, Y. (2011). A 0.5-V 1.13-μW/channel neural recording interface with digital multiplexing scheme. European Solid-State Circuits Conference : 219-222. ScholarBank@NUS Repository.
Abstract: This paper presents a power-efficient system architecture for the design of multiple-channel neural recording interface. A new multiple-channel SAR ADC is proposed to facilitate multiplexing among channels, thus eliminates the need for analog multiplexer and associated buffers. The proposed ADC is verified through a 16-channel recording chip fabricated in a standard 0.13-μm CMOS technology with an active area of 1.17 mm2. The chip consumes 18 μW from a 0.5-V supply and attains a noise efficiency factor of 3.09. The average per channel power and area are 1.13 μW and 0.073 mm2, respectively, which are the lowest among existing multiple-channel designs. © 2011 IEEE.
Source Title: European Solid-State Circuits Conference
ISBN: 9781457707018
ISSN: 19308833
DOI: 10.1109/ESSCIRC.2011.6044946
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