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|Title:||50-250 MHz ΔΣ DLL for clock synchronization||Authors:||Cheng, S.-J.
delay-locked loop (DLL)
second order adaptive filter
|Issue Date:||Nov-2010||Citation:||Cheng, S.-J., Qiu, L., Zheng, Y., Heng, C.-H. (2010-11). 50-250 MHz ΔΣ DLL for clock synchronization. IEEE Journal of Solid-State Circuits 45 (11) : 2445-2456. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2010.2072591||Abstract:||A ΔΣ DLL targeted for clock synchronization has been proposed. Unlike other existing ΔΣ DLL designs, the proposed DLL makes use of the ΔΣ dithering in the feedback path rather than at the input, which eliminates the need of additional multi-phase generator, and hence simplifies the architecture and improves the jitter performance. It also employs a second order adaptive filter to achieve dynamic loop bandwidth control for different operating frequencies as well as a unique antiharmonic detector to avoid false locking. Clock synchronization is achieved in two steps. During the coarse tuning step, the delay edge from DLL that closely matched to the incoming clock is first determined. In subsequent fine tuning step, a successive approximation method is then employed to quickly shift the selected delay edge to achieve synchronization with the incoming clock. Fabricated in 0.35 μ m CMOS technology, the ΔΣ DLL core can operate from 50 to 250 MHz with a delay step resolution of 15 ps and occupy only 0.4 mm2. It draws about 6.9 mA from 3 V supply at 200 MHz and exhibits an rms jitter of 2.1 ps. © 2010 IEEE.||Source Title:||IEEE Journal of Solid-State Circuits||URI:||http://scholarbank.nus.edu.sg/handle/10635/83302||ISSN:||00189200||DOI:||10.1109/JSSC.2010.2072591|
|Appears in Collections:||Staff Publications|
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