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Please use this identifier to cite or link to this item: https://doi.org/10.1109/TED.2007.900680
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dc.titleP-Type floating gate for retention and P/E window improvement of flash memory devices
dc.contributor.authorShen, C.
dc.contributor.authorPu, J.
dc.contributor.authorLi, M.-F.
dc.contributor.authorCho, B.J.
dc.date.accessioned2014-10-07T04:35:21Z
dc.date.available2014-10-07T04:35:21Z
dc.date.issued2007-08
dc.identifier.citationShen, C., Pu, J., Li, M.-F., Cho, B.J. (2007-08). P-Type floating gate for retention and P/E window improvement of flash memory devices. IEEE Transactions on Electron Devices 54 (8) : 1910-1917. ScholarBank@NUS Repository. https://doi.org/10.1109/TED.2007.900680
dc.identifier.issn00189383
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82943
dc.description.abstractA Flash memory with a lightly doped p-type floating gate is proposed, which improves charge retention and programming/erase (P/E) Vth window. Improvement in P/E window is enhanced for cells with smaller capacitance coupling ratio, which is important for future scaled Flash memory cells. Both device simulation and experimental verification are presented. © 2007 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TED.2007.900680
dc.sourceScopus
dc.subjectCoupling ratio (CR)
dc.subjectElectrically erasable programmable read-only memory (EEPROM)
dc.subjectFlash memory
dc.subjectFloating gate
dc.subjectP-type
dc.subjectRetention
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TED.2007.900680
dc.description.sourcetitleIEEE Transactions on Electron Devices
dc.description.volume54
dc.description.issue8
dc.description.page1910-1917
dc.description.codenIETDA
dc.identifier.isiut000248390600013
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