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Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2007.902086
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dc.titleBorder-trap characterization in high-κ strained-Si MOSFETs
dc.contributor.authorMaji, D.
dc.contributor.authorDuttagupta, S.P.
dc.contributor.authorRao, V.R.
dc.contributor.authorYeo, C.C.
dc.contributor.authorCho, B.-J.
dc.date.accessioned2014-10-07T04:24:25Z
dc.date.available2014-10-07T04:24:25Z
dc.date.issued2007-08
dc.identifier.citationMaji, D., Duttagupta, S.P., Rao, V.R., Yeo, C.C., Cho, B.-J. (2007-08). Border-trap characterization in high-κ strained-Si MOSFETs. IEEE Electron Device Letters 28 (8) : 731-733. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2007.902086
dc.identifier.issn07413106
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/82018
dc.description.abstractIn this letter, we focus on the border-trap characterization of TaN/ HfO2/Si and TaN/HfO2/strained-Si/Si0.8 Ge0.2 n-channel MOSFET devices. The equivalent oxide thickness for the gate dielectrics is 2 nm. Drain-current hysteresis method is used to characterize the border traps, and it is found that border traps are higher in the case of high-κ films on strained-Si/ Si0.8Ge0.2. These results are also verified by the 1/f-noise measurements. Possible reasons for the degraded interface quality of high-κ films on strained-Si are also proposed. © 2007 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/LED.2007.902086
dc.sourceScopus
dc.subject1/f noise
dc.subjectBorder traps
dc.subjectCharge pumping
dc.subjectHysteresis
dc.subjectInterface trapping
dc.subjectStrained-Si
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/LED.2007.902086
dc.description.sourcetitleIEEE Electron Device Letters
dc.description.volume28
dc.description.issue8
dc.description.page731-733
dc.description.codenEDLED
dc.identifier.isiut000248315400021
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