Please use this identifier to cite or link to this item: https://doi.org/10.1109/TVLSI.2013.2265265
DC FieldValue
dc.titleAverage-8T differential-sensing subthreshold SRAM with bit interleaving and 1k bits per bitline
dc.contributor.authorKhayatzadeh, M.
dc.contributor.authorLian, Y.
dc.date.accessioned2014-10-07T04:24:09Z
dc.date.available2014-10-07T04:24:09Z
dc.date.issued2014
dc.identifier.citationKhayatzadeh, M., Lian, Y. (2014). Average-8T differential-sensing subthreshold SRAM with bit interleaving and 1k bits per bitline. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5) : 971-982. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2013.2265265
dc.identifier.issn10638210
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/81997
dc.description.abstractThis paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including: 1) the differential and data-independent-leakage read port that facilitates robust and faster read operation and alleviates issues in the half-selected cell (pseudo-write) while reducing the area compared to the conventional 8T cell and 2) the various configurations from 14T for a baseline cell to 6.5T for an area-efficient 16-bit cell. These configurations reduce the overall bitcell area and enable low operating voltage. Two memory blocks based on the proposed architecture at the size of 16 and 64 kb, respectively, are fabricated in 0.13- μm CMOS process. The 64 kb prototype has an active area of 0.512 mm2 which is 16% less than that of the conventional 8T-cell-based design. The chip is fully functional for the read operation with 260 mV at 245 kHz and 270 mV for the write operation at 1 MHz. It can hold data down to 170 mV where the standby power consumption is only 884 nW. © 1993-2012 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/TVLSI.2013.2265265
dc.sourceScopus
dc.subjectAverage-8T
dc.subjectbit interleaving
dc.subjectdifferential
dc.subjectSRAM
dc.subjectsubthreshold
dc.subjectultralow power.
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/TVLSI.2013.2265265
dc.description.sourcetitleIEEE Transactions on Very Large Scale Integration (VLSI) Systems
dc.description.volume22
dc.description.issue5
dc.description.page971-982
dc.description.codenIEVSE
dc.identifier.isiut000337159500002
Appears in Collections:Staff Publications

Show simple item record
Files in This Item:
There are no files associated with this item.

SCOPUSTM   
Citations

22
checked on Nov 18, 2020

WEB OF SCIENCETM
Citations

17
checked on Nov 18, 2020

Page view(s)

83
checked on Nov 23, 2020

Google ScholarTM

Check

Altmetric


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.