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|dc.title||Average-8T differential-sensing subthreshold SRAM with bit interleaving and 1k bits per bitline|
|dc.identifier.citation||Khayatzadeh, M., Lian, Y. (2014). Average-8T differential-sensing subthreshold SRAM with bit interleaving and 1k bits per bitline. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (5) : 971-982. ScholarBank@NUS Repository. https://doi.org/10.1109/TVLSI.2013.2265265|
|dc.description.abstract||This paper presents a new average-8T write/read decoupled (A8T-WRD) SRAM architecture for low-power sub/near-threshold SRAM in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including: 1) the differential and data-independent-leakage read port that facilitates robust and faster read operation and alleviates issues in the half-selected cell (pseudo-write) while reducing the area compared to the conventional 8T cell and 2) the various configurations from 14T for a baseline cell to 6.5T for an area-efficient 16-bit cell. These configurations reduce the overall bitcell area and enable low operating voltage. Two memory blocks based on the proposed architecture at the size of 16 and 64 kb, respectively, are fabricated in 0.13- μm CMOS process. The 64 kb prototype has an active area of 0.512 mm2 which is 16% less than that of the conventional 8T-cell-based design. The chip is fully functional for the read operation with 260 mV at 245 kHz and 270 mV for the write operation at 1 MHz. It can hold data down to 170 mV where the standby power consumption is only 884 nW. © 1993-2012 IEEE.|
|dc.contributor.department||ELECTRICAL & COMPUTER ENGINEERING|
|dc.description.sourcetitle||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|Appears in Collections:||Staff Publications|
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