Please use this identifier to cite or link to this item: https://doi.org/10.1109/JSSC.2004.835835
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dc.titleA 2.4-GHz dual-mode 0.18-μm CMOS transceiver for bluetooth and 802.11b
dc.contributor.authorCho, T.B.
dc.contributor.authorKang, D.
dc.contributor.authorHeng, C.-H.
dc.contributor.authorSong, B.S.
dc.date.accessioned2014-10-07T04:22:17Z
dc.date.available2014-10-07T04:22:17Z
dc.date.issued2004-11
dc.identifier.citationCho, T.B., Kang, D., Heng, C.-H., Song, B.S. (2004-11). A 2.4-GHz dual-mode 0.18-μm CMOS transceiver for bluetooth and 802.11b. IEEE Journal of Solid-State Circuits 39 (11) : 1916-1926. ScholarBank@NUS Repository. https://doi.org/10.1109/JSSC.2004.835835
dc.identifier.issn00189200
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/81838
dc.description.abstractHigh-level integration of the Bluetooth and 802.11b WLAN radio systems in the 2.4-GHz ISM band is demonstrated in scaled CMOS. A dual-mode RF transceiver IC implements all transmit and receive functions including the low-noise amplifier (LNA), 0-dBm power amplifier, up/down mixers, synthesizers, channel filtering, and limiting/automatic gain control for both standards in a single chip without doubling the required silicon area to reduce the combined system cost. This is achieved by sharing the frequency up/down conversion circuits in the RF section and performing the required baseband channel filtering and gain functions with just one set of reconfigurable channel filter and amplifier for both modes. A chip implemented in 0.18-μm CMOS occupies 4 × 4 mm 2 including pad and consumes 60 and 40 mA for RX and TX modes, respectively. The dual-mode receiver exhibits -80-dBm sensitivity at 0.1% BER in Bluetooth mode and at 12-dB SNR in WLAN mode.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/JSSC.2004.835835
dc.sourceScopus
dc.subjectBluetooth
dc.subjectComplex filter
dc.subjectDual mode
dc.subjectIEEE 802.11b
dc.subjectRF tranceivers
dc.subjectWireless LAN
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/JSSC.2004.835835
dc.description.sourcetitleIEEE Journal of Solid-State Circuits
dc.description.volume39
dc.description.issue11
dc.description.page1916-1926
dc.description.codenIJSCB
dc.identifier.isiut000224692400012
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