1. ScholarBank@NUS
  2. 1. Staff
  3. Staff Publications
Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/81368
DC FieldValue
dc.titleYield optimization by design centering & worst-case distance analysis
dc.contributor.authorSamudra, G.S.
dc.contributor.authorChen, H.M.
dc.contributor.authorChan, D.S.H.
dc.contributor.authorIbrahim, Yaacob
dc.date.accessioned2014-10-07T03:07:34Z
dc.date.available2014-10-07T03:07:34Z
dc.date.issued1999
dc.identifier.citationSamudra, G.S.,Chen, H.M.,Chan, D.S.H.,Ibrahim, Yaacob (1999). Yield optimization by design centering & worst-case distance analysis. Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors : 289-290. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/81368
dc.description.abstractProcess variations invariably give rise to a parametric yield below 100% for VLSI circuits. Improving the yield by choosing a set of optimum parameter values does not incur any extra cost, and it is a preferred method as it directly translates into profits. This paper presents an efficient and novel method to improve the VLSI parametric yield by selecting optimum parameter values. This method utilizes the Worst-Case Distance Analysis, Design Centering and Gradient-Dependent techniques. One circuit example is presented to demonstrate the optimization scheme.
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.contributor.departmentINDUSTRIAL & SYSTEMS ENGINEERING
dc.description.sourcetitleProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
dc.description.page289-290
dc.description.codenPIIPE
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

Show simple item record
Files in This Item:
There are no files associated with this item.

Google ScholarTM

Check


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.