Please use this identifier to cite or link to this item: https://doi.org/10.1109/12.166611
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dc.titleSingle-precision multiplier with reduced circuit complexity for signal processing applications
dc.contributor.authorLim, Y.C.
dc.date.accessioned2014-10-07T03:05:37Z
dc.date.available2014-10-07T03:05:37Z
dc.date.issued1992-10
dc.identifier.citationLim, Y.C. (1992-10). Single-precision multiplier with reduced circuit complexity for signal processing applications. IEEE Transactions on Computers 41 (10) : 1333-1336. ScholarBank@NUS Repository. https://doi.org/10.1109/12.166611
dc.identifier.issn00189340
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/81191
dc.description.abstractWhen two numbers are multiplied, a double-wordlength product is produced. In applications where only the single-precision product is required, the double-wordlength result is rounded to single-precision. Hence, in single-precision applications, it is not necessary to compute the least significant part of the product exactly. Instead, it is only necessary to estimate the carries generated in the computation of the least significant part that will ripple into the most significant part of the product. This will produce a single-precision multiplier with significantly reduced circuit complexity. Three novel methods for realizing this class of reduced complexity single-precision multipliers are introduced and their performance analyzed.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/12.166611
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.doi10.1109/12.166611
dc.description.sourcetitleIEEE Transactions on Computers
dc.description.volume41
dc.description.issue10
dc.description.page1333-1336
dc.description.codenITCOB
dc.identifier.isiutA1992JX25300013
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