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Please use this identifier to cite or link to this item: https://doi.org/10.1023/A:1008379905128
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dc.titleNovel voltage-tunable, low-voltage linear CMOS transconductor
dc.contributor.authorLai, W.H.
dc.contributor.authorZhang, X.W.
dc.contributor.authorLi, M.-F.
dc.date.accessioned2014-10-07T03:01:52Z
dc.date.available2014-10-07T03:01:52Z
dc.date.issued2000-07
dc.identifier.citationLai, W.H., Zhang, X.W., Li, M.-F. (2000-07). Novel voltage-tunable, low-voltage linear CMOS transconductor. Analog Integrated Circuits and Signal Processing 24 (2) : 123-128. ScholarBank@NUS Repository. https://doi.org/10.1023/A:1008379905128
dc.identifier.issn09251030
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/80841
dc.description.abstractA novel voltage-tunable, low-voltage linear CMOS transconductor design is described. The design is based on the improvement of the cross-coupled pairs. SPICE simulation results show that using BSIM models, MOSIS 2-μm n-well process parameters and a power supply of ± 2.5 V, the linearity error is less than 0.4% over a differential input voltage range of ± 1.2 V. The THD for a differential input voltage of 1 Vpp at 1 kHz is 1.3%.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1023/A:1008379905128
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.doi10.1023/A:1008379905128
dc.description.sourcetitleAnalog Integrated Circuits and Signal Processing
dc.description.volume24
dc.description.issue2
dc.description.page123-128
dc.description.codenAICPE
dc.identifier.isiut000089553300004
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