Please use this identifier to cite or link to this item: https://doi.org/10.1109/55.644078
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dc.titleInvestigation of interface traps in LDD pMOST's by the DCIV method
dc.contributor.authorJie, B.B.
dc.contributor.authorLi, M.F.
dc.contributor.authorLou, C.L.
dc.contributor.authorChim, W.K.
dc.contributor.authorChan, D.S.H.
dc.contributor.authorLo, K.F.
dc.date.accessioned2014-10-07T02:59:39Z
dc.date.available2014-10-07T02:59:39Z
dc.date.issued1997-12
dc.identifier.citationJie, B.B., Li, M.F., Lou, C.L., Chim, W.K., Chan, D.S.H., Lo, K.F. (1997-12). Investigation of interface traps in LDD pMOST's by the DCIV method. IEEE Electron Device Letters 18 (12) : 583-585. ScholarBank@NUS Repository. https://doi.org/10.1109/55.644078
dc.identifier.issn07413106
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/80634
dc.description.abstractInterface traps in submicron buried-channel LDD pMOST's, generated under different stress conditions, are investigated by the direct-current current-voltage (DCIV) technique. Two peaks C and D in the DCIV spectrum are found corresponding to interface traps generated in the channel region and in the LDD region respectively. The new DCIV results clarify certain issues of the underlying mechanisms involved on hot-carrier degradation in LDD pMOST's. Under channel hot-carrier stress conditions, the hot electron injection and electron trapping in the oxide occurs for all stressing gate voltage. However, the electron injection induced interface trap spatial location changes from the LDD region to the channel region when the stressing gate voltage changes from low to high.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/55.644078
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.doi10.1109/55.644078
dc.description.sourcetitleIEEE Electron Device Letters
dc.description.volume18
dc.description.issue12
dc.description.page583-585
dc.description.codenEDLED
dc.identifier.isiutA1997YH55200003
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