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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/80330
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dc.titleComposite step-graded collector of InP/InGaAs/lnP DHBT for minimised carrier blocking
dc.contributor.authorChor, E.F.
dc.contributor.authorPeng, C.J.
dc.date.accessioned2014-10-07T02:56:20Z
dc.date.available2014-10-07T02:56:20Z
dc.date.issued1996-07-18
dc.identifier.citationChor, E.F.,Peng, C.J. (1996-07-18). Composite step-graded collector of InP/InGaAs/lnP DHBT for minimised carrier blocking. Electronics Letters 32 (15) : 1409-1410. ScholarBank@NUS Repository.
dc.identifier.issn00135194
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/80330
dc.description.abstractA composite step-graded collector of InP/InGaAs/InP DHBT has been investigated for minimised carrier blocking. The optimised collector has the following sub-layers: a 100Å n- InGaAs layer; three 200Å n- InGaAsP layers; and a 100Å, n = 3 × 1017cm-3 InP layer, and the rest are n- InP. The InGaAsP layers should be chosen to give approximately equal band offset at the heterointerfaces.
dc.sourceScopus
dc.subjectHeterojunction bipolar transistors
dc.subjectSemiconductor devices
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleElectronics Letters
dc.description.volume32
dc.description.issue15
dc.description.page1409-1410
dc.description.codenELLEA
dc.identifier.isiutNOT_IN_WOS
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