Please use this identifier to cite or link to this item: https://doi.org/10.1109/55.748912
DC FieldValue
dc.titleA New Model for the Post-Stress Interface Trap Generation in Hot-Carrier Stressed P-MOSFET's
dc.contributor.authorAng, D.S.
dc.contributor.authorLing, C.H.
dc.date.accessioned2014-10-07T02:55:45Z
dc.date.available2014-10-07T02:55:45Z
dc.date.issued1999-03
dc.identifier.citationAng, D.S., Ling, C.H. (1999-03). A New Model for the Post-Stress Interface Trap Generation in Hot-Carrier Stressed P-MOSFET's. IEEE Electron Device Letters 20 (3) : 135-137. ScholarBank@NUS Repository. https://doi.org/10.1109/55.748912
dc.identifier.issn07413106
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/80278
dc.description.abstractA new insight into the post-stress interface trap (Nit) generation in hot-electron stressed p-MOSFET's is presented.Nit generation is suppressed for positive oxide field but enhanced for negative oxide field. This observation provides strong support for a two-carrier model, involving the recombination between trapped electrons and inversion holes. While post-stress interface instability has generally been associated with hole trapping and hydrogen transport, our results clearly show the importance of electron traps on the long term stability of the Si-SiO2 interface, and that the two-carrier model provides a consistent explanation for post-stress Nit generation in p-MOSFET's stressed under hot-electron injection.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/55.748912
dc.sourceScopus
dc.subjectElectron traps
dc.subjectHot-carrier degradation
dc.subjectMOSFET's
dc.subjectPost-stress interface trap generation
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.contributor.departmentBACHELOR OF TECHNOLOGY PROGRAMME
dc.description.doi10.1109/55.748912
dc.description.sourcetitleIEEE Electron Device Letters
dc.description.volume20
dc.description.issue3
dc.description.page135-137
dc.description.codenEDLED
dc.identifier.isiut000078910800010
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