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|dc.title||120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit|
|dc.identifier.citation||Xu, S., Gan, K.P., Samudra, G.S., Liang, Y.C., Sin, J.K.O. (2000-10). 120 V interdigitated-drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit. IEEE Transactions on Electron Devices 47 (10) : 1980-1985. ScholarBank@NUS Repository. https://doi.org/10.1109/16.870584|
|dc.description.abstract||A new device structure named IDLDMOS is proposed to overcome the power LDMOS limit (R on,sp ∝ BV dss 2.5). The concept is based on replacing LDMOS lightly doped n-drift region by moderately doped alternating p and n layers of suitable dimension and doping. Off state requirement is achieved by mutual lateral-depletion of the alternating layers. Using small identical lateral width for both p and n layers, a doping concentration of up to two orders of magnitude higher than n-drift concentration in a conventional case can be achieved to reduce the on-resistance R on. The simulated 120 V IDLDMOS on SOI substrate has shown a R on value that is about 38% of the corresponding R on value of a conventional n - LDD type LDMOS. At a R on,sp value of 1.15 mΩ-cm 2 with BV dss of 124 V, IDLDMOS has exceeded the conventional LDMOS limit. Compared to conventional LDMOS, IDLDMOS is less prone to quasisaturation at high gate and drain voltage due to its higher drain doping. Isothermal simulation has shown that there was no deterioration in both ac and transient performance between the two devices. Nevertheless, the lower V d,sat of IDLDMOS is expected to yield a higher g m at the same level of current conduction as in the conventional structure.|
|dc.description.sourcetitle||IEEE Transactions on Electron Devices|
|Appears in Collections:||Staff Publications|
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