Please use this identifier to cite or link to this item: https://doi.org/10.7873/DATE2014.040
DC FieldValue
dc.titleWCET-Centric dynamic instruction cache locking
dc.contributor.authorDing, H.
dc.contributor.authorLiang, Y.
dc.contributor.authorMitra, T.
dc.date.accessioned2014-07-04T03:16:10Z
dc.date.available2014-07-04T03:16:10Z
dc.date.issued2014
dc.identifier.citationDing, H., Liang, Y., Mitra, T. (2014). WCET-Centric dynamic instruction cache locking. Proceedings -Design, Automation and Test in Europe, DATE : -. ScholarBank@NUS Repository. https://doi.org/10.7873/DATE2014.040
dc.identifier.isbn9783981537024
dc.identifier.issn15301591
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/78426
dc.description.abstractCache locking is an effective technique to improve timing predictability in real-time systems. In static cache locking, the locked memory blocks remain unchanged throughout the program execution. Thus static locking may not be effective for large programs where multiple memory blocks are competing for few cache lines available for locking. In comparison, dynamic cache locking overcomes cache space limitation through time-multiplexing of locked memory blocks. Prior dynamic locking technique partitions the program into regions and takes independent locking decisions for each region. We propose a flexible loop-based dynamic cache locking approach. We not only select the memory blocks to be locked but also the locking points (e.g., loop level). We judiciously allow memory blocks from the same loop to be locked at different program points for WCET improvement. We design a constraint-based approach that incorporates a global view to decide on the number of locking slots at each loop entry point and then select the memory blocks to be locked for each loop. Experimental evaluation shows that our dynamic cache locking approach achieves substantial improvement of WCET compared to prior techniques. © 2014 EDAA.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.7873/DATE2014.040
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentCOMPUTER SCIENCE
dc.description.doi10.7873/DATE2014.040
dc.description.sourcetitleProceedings -Design, Automation and Test in Europe, DATE
dc.description.page-
dc.identifier.isiutNOT_IN_WOS
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