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Title: Precise micro-architectural modeling for WCET analysis via AI+SAT
Authors: Banerjee, A.
Chattopadhyay, S.
Roychoudhury, A. 
Issue Date: 2013
Citation: Banerjee, A.,Chattopadhyay, S.,Roychoudhury, A. (2013). Precise micro-architectural modeling for WCET analysis via AI+SAT. Real-Time Technology and Applications - Proceedings : 87-96. ScholarBank@NUS Repository.
Abstract: Hard real-time systems are required to meet critical deadlines. Worst case execution time (WCET) is therefore an important metric for the system level schedulability analysis of hard real-time systems. However, performance enhancing features of a processor (e.g. pipeline, caches) makes WCET analysis a very difficult problem. In this paper, we propose a novel approach to combine abstract interpretation (AI) and satisfiability (SAT) checking (hence the name AI+SAT) for different varieties of micro-architectural modeling. Our work in this paper is inspired by the research advances in program flow analysis(e.g. infeasible path analysis). We show that the accuracy of WCET estimates can be improved in a scalable fashion by using SAT checkers to integrate infeasible path analysis results into micro-architectural modeling. Our modeling is implemented on top of the Chronos WCET analysis tool and we improve the accuracy of WCET estimates for instruction cache, data cache, branch predictors and shared caches. © 2013 IEEE.
Source Title: Real-Time Technology and Applications - Proceedings
ISBN: 9781479901869
ISSN: 10801812
DOI: 10.1109/RTAS.2013.6531082
Appears in Collections:Staff Publications

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