Study On IN0.53GA0.47AS MOS Devices with Plasma-Ph3/N2 Treatment and Device Structure Optimization

Abstract

Issues with high-k/In0.53Ga0.47As gate stack which is the high interface trap density resulting in gate stacks with low mobility, poor gate stack thermal stability and large gate leakage has been studied. Plasma-PH3/N2 treatment on HfAlO In0.53Ga0.47As MOSFET has been used to address these issues, revealing gate stack with good thermal stability up till 800?C. The improvements of peak mobility of this passivated device is attributed to the reduced trap states in the upper half of the bandgap, due to reduced free As, resulting in reduced Coulombic scattering compared to non-passivated device. The existence of a thicker passivation layer of passivated device reduces the soft optical phonon scattering contributed by the HfAlO and is effective in reducing interface dipole scattering at high E-field. Further optimization suitable for sub-22nm node In0.53Ga0.47As MOSFETs have been simulated using TCAD, using RSD structure with thin channel of 3nm thickness, high-k spacers, as well as with and without heterostructure.