Optimization of reliability of wafer level copper column interconnections using a variable compliance interconnect design

Abstract

This paper describes a finite element parametric study of the reliability of the solder joints of a flip chip package in which the height H and diameter D of copper column interconnects are varied. It was found that when D was kept constant at 50μm while H was varied, from 25μm to 150μm, there was a local optimum at around H=50μm. Thus while the compliance of the interconnect with H=100μm was greater, it did not lead to a longer fatigue life. However, beyond H=125μm, any increase in length/compliance did lead to a longer fatigue life. Similarly, when the interconnect height H was kept constant at 150μm while the diameter D was varied from 15μm to 35μm, it was found that a local optimum existed at around D=25μm. Next a simulation was conducted in which the height of the interconnects H was kept constant at 150μm while the diameter D on the same chip was decreased continuously from 35μm at the center to 15μm at the perimeter of the chip. It was found that this case where the compliance is low at the center and high at the perimeter of the chip gave fatigue lives which were more than double that of the local optimum case mentioned above where D was constant at 25μm. Hence, an interconnect design where the compliance of the interconnects on the same chip is varied from a low value at the center to a high value at the perimeter will lead to optimum reliability of the critical solder joint. © 2006 IEEE.