New multiple-function logic family

Abstract

A novel technique is presented for the design of a multiple-function logic (MFL) circuit which generates several Boolean functions simultaneously and shares the transistors implementing the common subexpression of these Boolean functions. For certain circuits, this approach requires fewer transistors and reduces the gate delays compared with the conventional approach where the common subexpression is implemented as a new intermediate function, shared by other gates to generate the required outputs. The application of the technique to a CMOS domino logic 4-b carry-lookahead generator and an nMOS 1-of-8 decoder results in savings of 45.0% and 42.5%, respectively, in the number of transistors needed.