Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/72792
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dc.titleNew multiple-function logic family
dc.contributor.authorTan, Y.K.
dc.contributor.authorLim, Y.C.
dc.contributor.authorKwok, C.Y.
dc.contributor.authorLing, C.H.
dc.date.accessioned2014-06-19T05:12:02Z
dc.date.available2014-06-19T05:12:02Z
dc.date.issued1989
dc.identifier.citationTan, Y.K.,Lim, Y.C.,Kwok, C.Y.,Ling, C.H. (1989). New multiple-function logic family. Proceedings - IEEE International Symposium on Circuits and Systems 2 : 965-968. ScholarBank@NUS Repository.
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/72792
dc.description.abstractA novel technique is presented for the design of a multiple-function logic (MFL) circuit which generates several Boolean functions simultaneously and shares the transistors implementing the common subexpression of these Boolean functions. For certain circuits, this approach requires fewer transistors and reduces the gate delays compared with the conventional approach where the common subexpression is implemented as a new intermediate function, shared by other gates to generate the required outputs. The application of the technique to a CMOS domino logic 4-b carry-lookahead generator and an nMOS 1-of-8 decoder results in savings of 45.0% and 42.5%, respectively, in the number of transistors needed.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.volume2
dc.description.page965-968
dc.description.codenPICSD
dc.identifier.isiutNOT_IN_WOS
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