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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/72642
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dc.titleFolded gate LDMOS with low on-resistance and high transconductance
dc.contributor.authorXu, S.
dc.contributor.authorZhu, Y.
dc.contributor.authorFoo, P.-D.
dc.contributor.authorLiang, Y.C.
dc.contributor.authorSin, J.K.O.
dc.date.accessioned2014-06-19T05:10:21Z
dc.date.available2014-06-19T05:10:21Z
dc.date.issued2000
dc.identifier.citationXu, S.,Zhu, Y.,Foo, P.-D.,Liang, Y.C.,Sin, J.K.O. (2000). Folded gate LDMOS with low on-resistance and high transconductance. IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD) : 55-56. ScholarBank@NUS Repository.
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/72642
dc.description.abstractIn this paper, a novel LDMOSFET is proposed with low on-resistance and high transconductance. The silicon substrate surface is trenched by using an extra mask, resulting in a folded gate structure. The channel density is doubled in the experiment. With the Folded Gate LDMOS (FG-gate LDMOS) concept, the on-resistance was reduced by 40%, while the transconductance was improved by 80%. The significance of the folded gate concept will be available for CMOS and other MOS-gated devices.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentINSTITUTE OF MICROELECTRONICS
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleIEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD)
dc.description.page55-56
dc.description.codenPISDE
dc.identifier.isiutNOT_IN_WOS
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