Comparative study of charge trapping effects in LDD surface-channel and buried-channel PMOS transistors using charge profiling and threshold voltage shift measurements

Abstract

Extracted charge profiles of lightly-doped drain (LDD) surface-channel and buried-channel pMOS devices stressed under hot-carrier injection conditions reveal predominant electron trapping near the gate edge at the drain region in both cases. From threshold voltage measurements, there is some evidence of hole trapping after long stress times in surface-channel pMOSFETs, but not in buried-channel devices. Hot-electron trapping is the dominant degradation mechanism in buried-channel LDD pMOSFETs. For surface-channel LDD pMOSFETs, large concentrations of electron traps near the gate edge were found.