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DC Field | Value | |
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dc.title | Synthesis and electronic application of germanium nanocrystals in silicon oxide matrix | |
dc.contributor.author | Choi, W.K. | |
dc.contributor.author | Chim, W.K. | |
dc.contributor.author | Chew, H.G. | |
dc.date.accessioned | 2014-06-19T03:29:20Z | |
dc.date.available | 2014-06-19T03:29:20Z | |
dc.date.issued | 2007 | |
dc.identifier.citation | Choi, W.K.,Chim, W.K.,Chew, H.G. (2007). Synthesis and electronic application of germanium nanocrystals in silicon oxide matrix. Materials Research Society Symposium Proceedings 959 : 95-100. ScholarBank@NUS Repository. | |
dc.identifier.isbn | 9781604234343 | |
dc.identifier.issn | 02729172 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/71920 | |
dc.description.abstract | The size of germanium (Ge) nanocrystals in a trilayer memory device structure was controlled by varying the thickness of the middle co-sputtered Ge plus silicon oxide layer. Such confinement of nanocrystals was not effective in a trilayer structure with a pure Ge middle layer. Significant diffusion of Ge atoms through the tunnel oxide or rapid thermal oxide (RTO) layer and into the silicon substrate was observed when the RTO layer thickness of the trilayer structure was reduced. This resulted in no (or very few) nanocrystals formed in the system. A higher charge storage capability was obtained from devices with a thinner RTO layer. © 2007 Materials Research Society. | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.sourcetitle | Materials Research Society Symposium Proceedings | |
dc.description.volume | 959 | |
dc.description.page | 95-100 | |
dc.description.coden | MRSPD | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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