Please use this identifier to cite or link to this item:
https://doi.org/10.1109/VLSIT.2008.4588551
DC Field | Value | |
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dc.title | Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance | |
dc.contributor.author | Lee, R.T.-P. | |
dc.contributor.author | Koh, A.T.-Y. | |
dc.contributor.author | Fang, W.-W. | |
dc.contributor.author | Tan, K.-M. | |
dc.contributor.author | Lim, A.E.-J. | |
dc.contributor.author | Liow, T.-Y. | |
dc.contributor.author | Chow, S.-Y. | |
dc.contributor.author | Yong, A.M. | |
dc.contributor.author | Hoong, S.W. | |
dc.contributor.author | Lo, G.-Q. | |
dc.contributor.author | Samudra, G.S. | |
dc.contributor.author | Chi, D.-Z. | |
dc.contributor.author | Yeo, Y.-C. | |
dc.date.accessioned | 2014-06-19T03:20:42Z | |
dc.date.available | 2014-06-19T03:20:42Z | |
dc.date.issued | 2008 | |
dc.identifier.citation | Lee, R.T.-P.,Koh, A.T.-Y.,Fang, W.-W.,Tan, K.-M.,Lim, A.E.-J.,Liow, T.-Y.,Chow, S.-Y.,Yong, A.M.,Hoong, S.W.,Lo, G.-Q.,Samudra, G.S.,Chi, D.-Z.,Yeo, Y.-C. (2008). Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance. Digest of Technical Papers - Symposium on VLSI Technology : 28-29. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/VLSIT.2008.4588551" target="_blank">https://doi.org/10.1109/VLSIT.2008.4588551</a> | |
dc.identifier.isbn | 9781424418053 | |
dc.identifier.issn | 07431562 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/71171 | |
dc.description.abstract | We have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20 % reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement. © 2008 IEEE. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/VLSIT.2008.4588551 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/VLSIT.2008.4588551 | |
dc.description.sourcetitle | Digest of Technical Papers - Symposium on VLSI Technology | |
dc.description.page | 28-29 | |
dc.description.coden | DTPTE | |
dc.identifier.isiut | 000259116200010 | |
Appears in Collections: | Staff Publications |
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