Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIT.2008.4588551
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dc.titleNovel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance
dc.contributor.authorLee, R.T.-P.
dc.contributor.authorKoh, A.T.-Y.
dc.contributor.authorFang, W.-W.
dc.contributor.authorTan, K.-M.
dc.contributor.authorLim, A.E.-J.
dc.contributor.authorLiow, T.-Y.
dc.contributor.authorChow, S.-Y.
dc.contributor.authorYong, A.M.
dc.contributor.authorHoong, S.W.
dc.contributor.authorLo, G.-Q.
dc.contributor.authorSamudra, G.S.
dc.contributor.authorChi, D.-Z.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-06-19T03:20:42Z
dc.date.available2014-06-19T03:20:42Z
dc.date.issued2008
dc.identifier.citationLee, R.T.-P.,Koh, A.T.-Y.,Fang, W.-W.,Tan, K.-M.,Lim, A.E.-J.,Liow, T.-Y.,Chow, S.-Y.,Yong, A.M.,Hoong, S.W.,Lo, G.-Q.,Samudra, G.S.,Chi, D.-Z.,Yeo, Y.-C. (2008). Novel and cost-efficient single metallic silicide integration solution with dual Schottky-barrier achieved by aluminum inter-diffusion for FinFET CMOS technology with enhanced performance. Digest of Technical Papers - Symposium on VLSI Technology : 28-29. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/VLSIT.2008.4588551" target="_blank">https://doi.org/10.1109/VLSIT.2008.4588551</a>
dc.identifier.isbn9781424418053
dc.identifier.issn07431562
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/71171
dc.description.abstractWe have developed a novel and cost-efficient silicide integration solution to achieve a hole barrier height of 215 meV and electron barrier height of 665 meV simultaneously with a single metallic silicide based on aluminum inter-diffusion. It is proposed that aluminum diffuses into PtSi and forms an alloy, which lowers the electron barrier height of PtSi due to a change in the intrinsic PtSi workfunction. Additionally, we have integrated platinum germanosilicide with an ultra-low hole barrier height of 215 meV in P-FinFETs to provide a 21% enhancement in drive current performance, which is attributed to the 20 % reduction in series resistance. We have also ascertained the compatibility of PtSiGe with laser thermal annealing for further performance enhancement. © 2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/VLSIT.2008.4588551
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/VLSIT.2008.4588551
dc.description.sourcetitleDigest of Technical Papers - Symposium on VLSI Technology
dc.description.page28-29
dc.description.codenDTPTE
dc.identifier.isiut000259116200010
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