Please use this identifier to cite or link to this item:
https://doi.org/10.1149/1.3122115
DC Field | Value | |
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dc.title | Development and characterization of high-k gate stack for Ge MOSFETs | |
dc.contributor.author | Xie, R. | |
dc.contributor.author | Zhu, C. | |
dc.date.accessioned | 2014-06-19T03:05:57Z | |
dc.date.available | 2014-06-19T03:05:57Z | |
dc.date.issued | 2009 | |
dc.identifier.citation | Xie, R.,Zhu, C. (2009). Development and characterization of high-k gate stack for Ge MOSFETs. ECS Transactions 19 (2) : 537-561. ScholarBank@NUS Repository. <a href="https://doi.org/10.1149/1.3122115" target="_blank">https://doi.org/10.1149/1.3122115</a> | |
dc.identifier.isbn | 9781566777100 | |
dc.identifier.issn | 19385862 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/69900 | |
dc.description.abstract | Recent developed high-permitivity (high-k) materials provide another opportunity to germanium (Ge) as a channel material in metal-oxide-semiconductor field-effect transistor applications. In this paper, developments of high-k/Ge gate stack have been reviewed. Various interface engineering processes including surface passivation techniques and post-gate treatments have been discussed. Physical and electrical characterizations have been made to evaluate the performance of interface engineered Ge MOS devices. © The Electrochemical Society. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1149/1.3122115 | |
dc.source | Scopus | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1149/1.3122115 | |
dc.description.sourcetitle | ECS Transactions | |
dc.description.volume | 19 | |
dc.description.issue | 2 | |
dc.description.page | 537-561 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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