Please use this identifier to cite or link to this item: https://doi.org/10.1149/1.3122115
DC FieldValue
dc.titleDevelopment and characterization of high-k gate stack for Ge MOSFETs
dc.contributor.authorXie, R.
dc.contributor.authorZhu, C.
dc.date.accessioned2014-06-19T03:05:57Z
dc.date.available2014-06-19T03:05:57Z
dc.date.issued2009
dc.identifier.citationXie, R.,Zhu, C. (2009). Development and characterization of high-k gate stack for Ge MOSFETs. ECS Transactions 19 (2) : 537-561. ScholarBank@NUS Repository. <a href="https://doi.org/10.1149/1.3122115" target="_blank">https://doi.org/10.1149/1.3122115</a>
dc.identifier.isbn9781566777100
dc.identifier.issn19385862
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/69900
dc.description.abstractRecent developed high-permitivity (high-k) materials provide another opportunity to germanium (Ge) as a channel material in metal-oxide-semiconductor field-effect transistor applications. In this paper, developments of high-k/Ge gate stack have been reviewed. Various interface engineering processes including surface passivation techniques and post-gate treatments have been discussed. Physical and electrical characterizations have been made to evaluate the performance of interface engineered Ge MOS devices. © The Electrochemical Society.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1149/1.3122115
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1149/1.3122115
dc.description.sourcetitleECS Transactions
dc.description.volume19
dc.description.issue2
dc.description.page537-561
dc.identifier.isiutNOT_IN_WOS
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