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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/69836
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dc.titleDesign and implementation of multiple addresses parallel transmission architecture for storage area network
dc.contributor.authorMeng, B.
dc.contributor.authorKhoo, P.B.T.
dc.contributor.authorChong, T.C.
dc.date.accessioned2014-06-19T03:05:14Z
dc.date.available2014-06-19T03:05:14Z
dc.date.issued2003
dc.identifier.citationMeng, B.,Khoo, P.B.T.,Chong, T.C. (2003). Design and implementation of multiple addresses parallel transmission architecture for storage area network. Digest of Papers - IEEE Symposium on Mass Storage Systems : 67-71. ScholarBank@NUS Repository.
dc.identifier.issn10519173
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/69836
dc.description.abstractIn this paper, we present a parallel transmission architecture for SAN. By using two schedulers on the destination and source addresses of packets, the load of multiple data flows between multiple devices can be balanced in an asymmetrical topology without using special hardware. The SAN performance could be scaled flexibly and additional fault tolerance feature is provided. The load balancing algorithms we provide can be easily implemented and the computation is efficient enough for high-speed transmission.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleDigest of Papers - IEEE Symposium on Mass Storage Systems
dc.description.page67-71
dc.description.codenDPISD
dc.identifier.isiutNOT_IN_WOS
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