Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/69603
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dc.titleCircuit model of elastomer probe for fine pitch wafer level package test applications
dc.contributor.authorJayabalan, J.
dc.contributor.authorOoi, B.L.
dc.contributor.authorLeong, M.S.
dc.contributor.authorIyer, M.K.
dc.date.accessioned2014-06-19T03:02:32Z
dc.date.available2014-06-19T03:02:32Z
dc.date.issued2005
dc.identifier.citationJayabalan, J.,Ooi, B.L.,Leong, M.S.,Iyer, M.K. (2005). Circuit model of elastomer probe for fine pitch wafer level package test applications. Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005 1 : 175-178. ScholarBank@NUS Repository.
dc.identifier.isbn0780395786
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/69603
dc.description.abstractA novel elastomer probe meant for wafer level packaged device test applications at multi-gigahertz frequencies given tight mechanical constraints such as very fine pitch (of the order of 100 micron) and large pin count (of thousands per square centimeter) is modeled by partial element equivalent circuit (PEEC) method. The model is verified through insertion loss and return loss measurements on a prototype coplanar probe. © 2005 IEEE.
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentMECHANICAL ENGINEERING
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.sourcetitleProceedings of 7th Electronics Packaging Technology Conference, EPTC 2005
dc.description.volume1
dc.description.page175-178
dc.identifier.isiutNOT_IN_WOS
Appears in Collections:Staff Publications

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