Please use this identifier to cite or link to this item: https://doi.org/10.1145/2038698.2038726
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dc.titleA hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs
dc.contributor.authorSingh, A.K.
dc.contributor.authorKumar, A.
dc.contributor.authorSrikanthan, T.
dc.date.accessioned2014-06-19T02:53:51Z
dc.date.available2014-06-19T02:53:51Z
dc.date.issued2011
dc.identifier.citationSingh, A.K.,Kumar, A.,Srikanthan, T. (2011). A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs. Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 : 175-184. ScholarBank@NUS Repository. <a href="https://doi.org/10.1145/2038698.2038726" target="_blank">https://doi.org/10.1145/2038698.2038726</a>
dc.identifier.isbn9781450307130
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/68843
dc.description.abstractModern embedded systems are based on Multiprocessor- Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A design-time methodology is applicable only to predefined set of applications with static behavior, which is incapable of handling dynamism in applications. On the other hand, a run-time approach can cater to the dynamism but cannot provide timing guarantees for all the applications due to large computation requirements at run-time. This paper presents a hybrid flow which performs compute intensive analysis at design-time to derive multiple resource-throughput trade-off points and selects one of these at runtime subject to available resources and desired throughput. Experimental results show that the design-time analysis is faster by 39%, provides better trade-off points and the runtime mapping is speeded up by 93% when compared to state-of-the-art techniques. Copyright © 2011 ACM.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1145/2038698.2038726
dc.sourceScopus
dc.subjectDesign-time analysis
dc.subjectMultiprocessor
dc.subjectRun-time mapping
dc.subjectSynchronous dataflow
dc.subjectThroughput
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1145/2038698.2038726
dc.description.sourcetitleEmbedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11
dc.description.page175-184
dc.identifier.isiutNOT_IN_WOS
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