Please use this identifier to cite or link to this item:
https://doi.org/10.1145/2038698.2038726
DC Field | Value | |
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dc.title | A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs | |
dc.contributor.author | Singh, A.K. | |
dc.contributor.author | Kumar, A. | |
dc.contributor.author | Srikanthan, T. | |
dc.date.accessioned | 2014-06-19T02:53:51Z | |
dc.date.available | 2014-06-19T02:53:51Z | |
dc.date.issued | 2011 | |
dc.identifier.citation | Singh, A.K.,Kumar, A.,Srikanthan, T. (2011). A hybrid strategy for mapping multiple throughput-constrained applications on MPSoCs. Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 : 175-184. ScholarBank@NUS Repository. <a href="https://doi.org/10.1145/2038698.2038726" target="_blank">https://doi.org/10.1145/2038698.2038726</a> | |
dc.identifier.isbn | 9781450307130 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/68843 | |
dc.description.abstract | Modern embedded systems are based on Multiprocessor- Systems-on-Chip (MPSoCs) to meet the strict timing deadlines of multiple applications. MPSoC resources must be utilized efficiently by mapping the applications in throughput-aware manner in order to meet throughput constraints for each of them. A design-time methodology is applicable only to predefined set of applications with static behavior, which is incapable of handling dynamism in applications. On the other hand, a run-time approach can cater to the dynamism but cannot provide timing guarantees for all the applications due to large computation requirements at run-time. This paper presents a hybrid flow which performs compute intensive analysis at design-time to derive multiple resource-throughput trade-off points and selects one of these at runtime subject to available resources and desired throughput. Experimental results show that the design-time analysis is faster by 39%, provides better trade-off points and the runtime mapping is speeded up by 93% when compared to state-of-the-art techniques. Copyright © 2011 ACM. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1145/2038698.2038726 | |
dc.source | Scopus | |
dc.subject | Design-time analysis | |
dc.subject | Multiprocessor | |
dc.subject | Run-time mapping | |
dc.subject | Synchronous dataflow | |
dc.subject | Throughput | |
dc.type | Conference Paper | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1145/2038698.2038726 | |
dc.description.sourcetitle | Embedded Systems Week 2011, ESWEEK 2011 - Proceedings of the 14th International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES'11 | |
dc.description.page | 175-184 | |
dc.identifier.isiut | NOT_IN_WOS | |
Appears in Collections: | Staff Publications |
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