Please use this identifier to cite or link to this item: https://doi.org/10.1109/ISCAS.2008.4541348
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dc.titleA HW CABAC encoder with efficient context access scheme for H.264/AVC
dc.contributor.authorTian, X.H.
dc.contributor.authorLe, T.M.
dc.contributor.authorJiang, X.
dc.contributor.authorLian, Y.
dc.date.accessioned2014-06-19T02:53:45Z
dc.date.available2014-06-19T02:53:45Z
dc.date.issued2008
dc.identifier.citationTian, X.H., Le, T.M., Jiang, X., Lian, Y. (2008). A HW CABAC encoder with efficient context access scheme for H.264/AVC. Proceedings - IEEE International Symposium on Circuits and Systems : 37-40. ScholarBank@NUS Repository. https://doi.org/10.1109/ISCAS.2008.4541348
dc.identifier.isbn9781424416844
dc.identifier.issn02714310
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/68835
dc.description.abstractIn this paper, we propose a hardware Context-based Binary Arithmetic Coder (CABAC) targeting the main profile of H.264/AVC standard. The encoder fully supports different coding modes including RDO coding. An efficient memory access scheme is proposed and shown to reduce context memory access rate, context memory size, and RDO context state backup and restore operation delay. Coding throughput of 1 bin/cycle is achieved by pipelined structure. The encoder is physical implemented with 362MHz clock frequency and power reduction technique is also utilized. ©2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ISCAS.2008.4541348
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ISCAS.2008.4541348
dc.description.sourcetitleProceedings - IEEE International Symposium on Circuits and Systems
dc.description.page37-40
dc.description.codenPICSD
dc.identifier.isiut000258532100011
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