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Title: A high-speed low-power D flip-flop
Authors: Chandrasekaran, R. 
Yong, L. 
Rana, R.S.
Issue Date: 2005
Citation: Chandrasekaran, R.,Yong, L.,Rana, R.S. (2005). A high-speed low-power D flip-flop. ASICON 2005: 2005 6th International Conference on ASIC, Proceedings 1 : 152-155. ScholarBank@NUS Repository.
Abstract: This paper proposes a new D flip-flop configuration based on Differential Cascode Voltage Switch with Pass-Gate Logic. The circuit is able to reduce the transition time from the input to output. The flip-flop was implemented in 0.18 μm CMOS technology. The flip-flop was simulated using HSPICE to assess the performance and was further evaluated by measurements on a test chip. The maximum operating frequency of the flip-flop is 5 GHz according to simulation. The test chip operates correctly at 3 GHz. This performance makes it one of the fastest flip-flops with a rail-to-rail input and voltage swing. © 2005 IEEE.
Source Title: ASICON 2005: 2005 6th International Conference on ASIC, Proceedings
ISBN: 0780392108
Appears in Collections:Staff Publications

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