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|Title:||A high normalized aggregate throughput SoC-based inverse integer transform design for H.264/AVC||Authors:||Do, T.T.T.
Inverse integer transform
|Issue Date:||2009||Citation:||Do, T.T.T.,Le, T.M. (2009). A high normalized aggregate throughput SoC-based inverse integer transform design for H.264/AVC. ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings : 453-456. ScholarBank@NUS Repository.||Abstract:||In this paper, a high normalized aggregate throughput system-on-chip-based inverse integer transform (IIT) module for H.264/AVC is proposed. Aggregate throughput involves calculation of delays due to both processing and I/O data transfer. Aggregate throughputs of reported designs with different data bus widths are normalized to facilitate performance comparison. The proposed IIT blocks is orchestrated - by a controller with 2 built-in-RAM DMACs - to perform both 4x4 and 8x8 transforms with supports for 2x2 and 4x4 Hadamard transforms of DC coefficients. Compared to the reported designs, the proposed IIT module achieves a high normalized aggregate throughput of 64 pixel-per-cycle and 15.6 Giga pixel-per-second, at 244MHz using 0.18μm technology.||Source Title:||ISIC-2009 - 12th International Symposium on Integrated Circuits, Proceedings||URI:||http://scholarbank.nus.edu.sg/handle/10635/68830||ISBN:||9789810824686|
|Appears in Collections:||Staff Publications|
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