A high normalized aggregate throughput SoC-based inverse integer transform design for H.264/AVC

Abstract

In this paper, a high normalized aggregate throughput system-on-chip-based inverse integer transform (IIT) module for H.264/AVC is proposed. Aggregate throughput involves calculation of delays due to both processing and I/O data transfer. Aggregate throughputs of reported designs with different data bus widths are normalized to facilitate performance comparison. The proposed IIT blocks is orchestrated - by a controller with 2 built-in-RAM DMACs - to perform both 4x4 and 8x8 transforms with supports for 2x2 and 4x4 Hadamard transforms of DC coefficients. Compared to the reported designs, the proposed IIT module achieves a high normalized aggregate throughput of 64 pixel-per-cycle and 15.6 Giga pixel-per-second, at 244MHz using 0.18μm technology.