Please use this identifier to cite or link to this item: https://doi.org/10.1109/VLSIC.2007.4342692
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dc.titleA CMOS readout circuit for silicon resonant accelerometer with 32-ppb bias stability
dc.contributor.authorHe, L.
dc.contributor.authorXu, Y.P.
dc.contributor.authorPalaniapan, M.
dc.date.accessioned2014-06-19T02:52:36Z
dc.date.available2014-06-19T02:52:36Z
dc.date.issued2007
dc.identifier.citationHe, L., Xu, Y.P., Palaniapan, M. (2007). A CMOS readout circuit for silicon resonant accelerometer with 32-ppb bias stability. IEEE Symposium on VLSI Circuits, Digest of Technical Papers : 146-147. ScholarBank@NUS Repository. https://doi.org/10.1109/VLSIC.2007.4342692
dc.identifier.isbn9784900784048
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/68732
dc.description.abstractThis paper describes a fully-differential CMOS readout circuit for silicon micro-resonant accelerometer. Tested with a SOI resonator, the readout chip sustains the oscillation at 110 kHz with a phase noise of -36dBc@1Hz and a bias stability of 0.0035Hz or 32ppb, which can be translated to an amplitude noise of 1Å/√Hz down to 0.05Hz and stability of 0.22Å up to 100 seconds. The chip is fabricated in a 0.35-um CMOS process and draws 5mA under a 3.3-V single supply.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/VLSIC.2007.4342692
dc.sourceScopus
dc.subjectBias stability
dc.subjectCMOS readout circuit
dc.subjectMEMS resonator
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/VLSIC.2007.4342692
dc.description.sourcetitleIEEE Symposium on VLSI Circuits, Digest of Technical Papers
dc.description.page146-147
dc.description.coden85PXA
dc.identifier.isiut000250541000054
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