Please use this identifier to cite or link to this item: https://doi.org/10.1109/ASSCC.2008.4708797
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dc.titleA 52 pJ/bit ook transmitter with adaptable data rate
dc.contributor.authorRaja, M.K.
dc.contributor.authorXu, Y.P.
dc.date.accessioned2014-06-19T02:52:22Z
dc.date.available2014-06-19T02:52:22Z
dc.date.issued2008
dc.identifier.citationRaja, M.K.,Xu, Y.P. (2008). A 52 pJ/bit ook transmitter with adaptable data rate. Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 : 341-344. ScholarBank@NUS Repository. <a href="https://doi.org/10.1109/ASSCC.2008.4708797" target="_blank">https://doi.org/10.1109/ASSCC.2008.4708797</a>
dc.identifier.isbn9781424426058
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/68712
dc.description.abstractA 433-MHz OOK transmitter with adaptable data rate is presented. The proposed circuit completely turns off the transmitter during the transmission of '0' and employs a speedup scheme to obtain high data rates and low wake up time. The data rate can be adjusted and adapted to the need of applications. Realized in a 0.35-μm CMOS technology, the OOK transmitter has a measured output power of -12.7dBm with a dc power consumption of 560 fiW under a 1-V power supply, and a data rate of 3 Mb/s, yielding an energy efficiency of 187 pJ/bit or 3.48 nJ/bit/mW if normalized to the transmitting power. When the proposed speed-up circuitry is enabled, data rate increases to 10 Mb/s, with a dc power consumption of 518 fiW achieving an energy efficiency of 52 pJ/bit or 0.97 nJ/bit/mW when normalized.©2008 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/ASSCC.2008.4708797
dc.sourceScopus
dc.typeConference Paper
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/ASSCC.2008.4708797
dc.description.sourcetitleProceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
dc.description.page341-344
dc.identifier.isiutNOT_IN_WOS
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