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|Title:||A 1-V 60-μ W 16-channel interface chip for implantable neural recording||Authors:||Liew, W.-S.
|Issue Date:||2009||Citation:||Liew, W.-S.,Zou, X.,Yao, L.,Lian, Y. (2009). A 1-V 60-μ W 16-channel interface chip for implantable neural recording. Proceedings of the Custom Integrated Circuits Conference : 507-510. ScholarBank@NUS Repository. https://doi.org/10.1109/CICC.2009.5280795||Abstract:||This paper presents a low-voltage low-power 16-channel interface chip dedicated for implantable neural signal recording. It consists of 16 front-end channels with tunable bandpass filtering and gain settings, multiplexed to a 10-bit SAR ADC for simultaneous recording. To comply with the implantation safety issue while maintaining comparable performance, the overall system is optimized to achieve low power dissipation and efficient power distribution among each individual blocks. A power efficient OTA topology is adopted in the front-end amplifier and a novel dual-capacitive-array SAR ADC is chosen to achieve better power efficiency. A prototype fabricated in a 0.35-μm CMOS technology achieves a NEF of 2.16 and THD of 0.53% at full output swing while providing output data rate of 16 kS/s per channel. The interface consumes 60.3-μW total power from a 1-V supply. © 2009 IEEE.||Source Title:||Proceedings of the Custom Integrated Circuits Conference||URI:||http://scholarbank.nus.edu.sg/handle/10635/68705||ISBN:||9781424440726||ISSN:||08865930||DOI:||10.1109/CICC.2009.5280795|
|Appears in Collections:||Staff Publications|
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