Please use this identifier to cite or link to this item:
https://doi.org/10.1109/55.998878
DC Field | Value | |
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dc.title | Hole tunneling current through oxynitride/oxide stack and the stack optimization for p-MOSFETs | |
dc.contributor.author | Yu, H.Y. | |
dc.contributor.author | Hou, Y.T. | |
dc.contributor.author | Li, M.F. | |
dc.contributor.author | Kwong, D.-L. | |
dc.date.accessioned | 2014-06-18T05:32:58Z | |
dc.date.available | 2014-06-18T05:32:58Z | |
dc.date.issued | 2002-05 | |
dc.identifier.citation | Yu, H.Y., Hou, Y.T., Li, M.F., Kwong, D.-L. (2002-05). Hole tunneling current through oxynitride/oxide stack and the stack optimization for p-MOSFETs. IEEE Electron Device Letters 23 (5) : 285-287. ScholarBank@NUS Repository. https://doi.org/10.1109/55.998878 | |
dc.identifier.issn | 07413106 | |
dc.identifier.uri | http://scholarbank.nus.edu.sg/handle/10635/67962 | |
dc.description.abstract | A systematic study on hole-tunneling current through both oxynitride and oxynitride/oxide (N/O) stack is for the first time presented based on a physical model. The calculations are in good agreement with the available experimental data. With a given equivalent oxide thickness (EOT), and under typical operating gate voltages (|V g| < 2 V), hole-tunneling current (essentially the gate current) is found to be lowest through the oxynitride or N/O stack with ∼33% of nitrogen (N). An optimized N/O stack structure with 33% (atomic percentage) nitrogen and with a 3 Å oxide layer for keeping acceptable channel interface quality is proposed to project the N/O gate dielectrics scaling limit using in MOSFETs. | |
dc.description.uri | http://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/55.998878 | |
dc.source | Scopus | |
dc.subject | Dielectric films | |
dc.subject | Hole tunneling | |
dc.subject | MOSFETs | |
dc.subject | Oxynitride/oxide (N/O) | |
dc.subject | Silicon oxynitrides | |
dc.type | Others | |
dc.contributor.department | ELECTRICAL ENGINEERING | |
dc.contributor.department | ELECTRICAL & COMPUTER ENGINEERING | |
dc.description.doi | 10.1109/55.998878 | |
dc.description.sourcetitle | IEEE Electron Device Letters | |
dc.description.volume | 23 | |
dc.description.issue | 5 | |
dc.description.page | 285-287 | |
dc.description.coden | EDLED | |
dc.identifier.isiut | 000175234700017 | |
Appears in Collections: | Staff Publications |
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