Simple programmable processor for decoding Reed-Solomon codes in compact disc devices at high speed

Abstract

The computational requirements of different decoding strategies for the error correction of the cross-interleaved Reed-Solomon code used in compact disc (CD) optical mass-storage devices are studied. From this investigation, an architecture for a simple programmable arithmetic processor suitable for rapidly and flexibly implementing the various time-domain decoding strategies is proposed. With current technology, it is envisaged that the fast processor will be able to correct four erasure byte errors or correct two byte errors at unknown locations in less than 4 μs. At this speed, a Reed-Solomon decoder for CD devices has a throughput of about 2 Mbytes/s. While it is fast, the processor can also be implemented as it consists of only two independent sets of registers, about 20 kbit of ROM for storing the values of some commonly used functions, a multiplier and an adder.