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Please use this identifier to cite or link to this item: https://scholarbank.nus.edu.sg/handle/10635/62388
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dc.titleLogarithmic time dependence of pMOSFET degradation observed from gate capacitance
dc.contributor.authorLing, C.H.
dc.contributor.authorYeow, Y.T.
dc.contributor.authorAh, L.K.
dc.contributor.authorYung, W.H.
dc.contributor.authorChoi, W.K.
dc.date.accessioned2014-06-17T06:50:30Z
dc.date.available2014-06-17T06:50:30Z
dc.date.issued1993-01-01
dc.identifier.citationLing, C.H.,Yeow, Y.T.,Ah, L.K.,Yung, W.H.,Choi, W.K. (1993-01-01). Logarithmic time dependence of pMOSFET degradation observed from gate capacitance. Electronics Letters 29 (4) : 418-420. ScholarBank@NUS Repository.
dc.identifier.issn00135194
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/62388
dc.description.abstractHot-carrier degradation in pMOSFETs is observed from an increase in gate overlap capacitance, due to trapped electrons in the gate oxide inverting a portion of the channel near the stressed junction. Logarithmic time growth of the overlap capacitance, and hence of the trapped charge, is reported.
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL ENGINEERING
dc.description.sourcetitleElectronics Letters
dc.description.volume29
dc.description.issue4
dc.description.page418-420
dc.description.codenELLEA
dc.identifier.isiutNOT_IN_WOS
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