Please use this identifier to cite or link to this item: https://doi.org/10.1063/1.3010303
DC FieldValue
dc.titleStudy of surface passivation of strained indium gallium arsenide by vacuum annealing and silane treatment
dc.contributor.authorChin, H.-C.
dc.contributor.authorWang, B.
dc.contributor.authorLim, P.-C.
dc.contributor.authorTang, L.-J.
dc.contributor.authorTung, C.-H.
dc.contributor.authorYeo, Y.-C.
dc.date.accessioned2014-06-17T03:07:20Z
dc.date.available2014-06-17T03:07:20Z
dc.date.issued2008
dc.identifier.citationChin, H.-C., Wang, B., Lim, P.-C., Tang, L.-J., Tung, C.-H., Yeo, Y.-C. (2008). Study of surface passivation of strained indium gallium arsenide by vacuum annealing and silane treatment. Journal of Applied Physics 104 (9) : -. ScholarBank@NUS Repository. https://doi.org/10.1063/1.3010303
dc.identifier.issn00218979
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/57540
dc.description.abstractA study of the surface passivation of strained InGaAs using vacuum annealing and silane (SiH4) passivation was reported for the first time. X-ray photoelectron spectroscopy reveals the elimination of As-O bond after vacuum annealing and SiH4 surface passivation. Vacuum annealing eliminated poor quality native oxide on InGaAs surface, while a thin silicon interfacial layer was formed by SiH4 treatment, therefore effectively preventing the InGaAs surface from exposure to an oxidizing ambient during high- k dielectric deposition. Transmission electron micrograph confirmed the existence of a thin oxidized silicon layer between high- k dielectric and InGaAs. By incorporating this surface technology during gate stack formation, TaN/HfAlO/InGaAs metal-oxide-semiconductor capacitors demonstrate superior C-V characteristics with negligible frequency dispersion, small hysteresis, and interface state density as low as (3.5× 1011) - (5.0× 1011) cm-2 eV-1. © 2008 American Institute of Physics.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1063/1.3010303
dc.sourceScopus
dc.typeArticle
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1063/1.3010303
dc.description.sourcetitleJournal of Applied Physics
dc.description.volume104
dc.description.issue9
dc.description.page-
dc.description.codenJAPIA
dc.identifier.isiut000260941700045
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