Please use this identifier to cite or link to this item: https://doi.org/10.1109/LED.2010.2047375
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dc.titleModeling of stress-retarded thermal oxidation of nonplanar silicon structures for realization of nanoscale devices
dc.contributor.authorMa, F.-J.
dc.contributor.authorRustagi, S.C.
dc.contributor.authorSamudra, G.S.
dc.contributor.authorZhao, H.
dc.contributor.authorSingh, N.
dc.contributor.authorLo, G.-Q.
dc.contributor.authorKwong, D.-L.
dc.date.accessioned2014-06-17T02:57:18Z
dc.date.available2014-06-17T02:57:18Z
dc.date.issued2010-07
dc.identifier.citationMa, F.-J., Rustagi, S.C., Samudra, G.S., Zhao, H., Singh, N., Lo, G.-Q., Kwong, D.-L. (2010-07). Modeling of stress-retarded thermal oxidation of nonplanar silicon structures for realization of nanoscale devices. IEEE Electron Device Letters 31 (7) : 719-721. ScholarBank@NUS Repository. https://doi.org/10.1109/LED.2010.2047375
dc.identifier.issn07413106
dc.identifier.urihttp://scholarbank.nus.edu.sg/handle/10635/56676
dc.description.abstractAccurate modeling of stress-retarded orientation-dependent 2-D oxidation is carried out by matching the experimental and simulated oxide thicknesses of silicon FIN nanostructures over a wide range of temperatures and times in dry oxygen. Experimentally observed initial oxidation rate enhancement, orientation-dependent stress retardation, and self-limiting phenomena are modeled, and a new universal stress retardation parameter set is obtained for the first time. The new parameter set has been validated against oxidation experiments presented here and those reported in the literature. Furthermore, the new model is used to explore silicon nanowire shape engineering. © 2010 IEEE.
dc.description.urihttp://libproxy1.nus.edu.sg/login?url=http://dx.doi.org/10.1109/LED.2010.2047375
dc.sourceScopus
dc.subject2-D oxidation
dc.subjectNanowire (NW)
dc.subjectorientation dependence
dc.subjectself-limiting
dc.subjectshape engineering
dc.subjectstress retardation
dc.typeArticle
dc.contributor.departmentSOLAR ENERGY RESEARCH INST OF S'PORE
dc.contributor.departmentELECTRICAL & COMPUTER ENGINEERING
dc.description.doi10.1109/LED.2010.2047375
dc.description.sourcetitleIEEE Electron Device Letters
dc.description.volume31
dc.description.issue7
dc.description.page719-721
dc.description.codenEDLED
dc.identifier.isiut000281833100029
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